The layer of oxide that insulates the gate from the other semiconductor regions of a MOS gated device is highly susceptible to damage when a large voltage is applied between the gate and source electrodes of the device. A damaged gate oxide layer between the device's gate and source region can lead to a short circuit between the gate and source region which will render the device non-operational. For typical MOS gated power devices, such as MOSFETS (metal-oxide-semiconductor field effect transistor), IGTS (insulated gate transistor), MCTS (MOS controlled thyristor), etc., this oxide layer thickness is on the order of 1000 angstroms and will usually break down at a voltage of about 80 volts. The oxide layer that insulates the gate from the source region may also have defects therein along its expanse, such as reduced thickness or small openings between the gate and source region. The oxide layer at the location of a defect can break down at voltages on the order of 40-50 volts to create a short circuit between the device's gate and source region. The probability that a defect may be present increases as the device size increases and as the oxide thickness decreases. Furthermore, it is desirable that the oxide layer be as thin as possible to enhance the transconductance of the device. While a thin oxide layer reduces losses and increases efficiency by lowering the on-resistance of the device, it also increases the vulnerability of the oxide layer to damage caused by voltage surges.
It is accordingly an object of the present invention to provide a self-protected MOS gated device which is not subject to the foregoing disadvantages. This method of self protection will differ from that typically employed by signal level MOS gated devices due to the higher gate voltage drive requirements of a power MOS gated device. This makes it impractical to use a standard N+P junction having a breakdown voltage less than 10 volts.
It is another object of the present invention to provide a new and improved protective clamp for a MOS gated device, formed integrally with the device without additional process steps, to protect the device against voltage surges.
A further object of the present invention is to provide a new and improved, self-protected MOS gated power device which is simple in construction and inexpensive to manufacture.
Still another object of the present invention is to provide a protective clamp for a MOS gated device that is integrated with the device, is readily responsive to voltage surges, and is reliable over a long service life.